1. Field of the Invention
The present invention relates to a process for manufacturing high-density MOS technology power devices, such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), and to a high-density MOS-technology power device integrated structure thus obtained.
2. Discussion of the Related Art
It is known that MOS-technology power devices are composed of a plurality of elementary functional units integrated in a semiconductor chip; each elementary functional unit forms an elementary vertical MOSFET which contributes a respective fraction to the overall power device current.
Conventionally, the elementary functional units are represented by polygonal-plan elementary cells, having a polygonal-plan P type region (called xe2x80x9cbody regionxe2x80x9d), formed in an Nxe2x88x92 semiconductor layer and comprising in turn a central P+ region (called xe2x80x9cdeep body regionxe2x80x9d) and a lateral Pxe2x88x92 channel region; an N+ polygonal annular source region is formed inside the P type body region. The polygonal annular portion of the body region between the external edge of the N+ source region and the edge of the body region is covered by a conductive layer (polysilicon gate) superimposed on an insulating layer (gate oxide) and forms a channel region of the elementary MOSFET. The polysilicon layer is covered by a dielectric layer, in which a contact window is opened to allow a superimposed conductive layer (source electrode) to come into contact with the N+ source region and the portion of the body region delimited by the inner edge of the N+ source region; this is necessary to prevent a parasitic bipolar junction transistor (with emitter, base and collector represented by the source region, the deep body region and the Nxe2x88x92 semiconductor layer) from being triggered on.
A conventional manufacturing process substantially provides for:
epitaxially growing the Nxe2x88x92 semiconductor layer over a heavily doped substrate of the N conductivity type, in the case of a power MOSFET, or of the P conductivity type, in the case of an IGBT;
maskedly implanting and diffusing a heavy dose of a P type dopant into selected regions of the N type layer, to form the deep body regions of the elementary cells (first mask);
thermally growing a thin oxide layer over the surface of the N type layer;
depositing a polysilicon layer over the thin oxide layer;
selectively etching the polysilicon layer and the thin oxide layer around the deep body regions (second mask);
implanting a low dose of a P type dopant using the polysilicon and oxide layers as a mask;
diffusing the P type dopant to form channel regions extending under the thin oxide layer;
maskedly implanting a heavy dose of an N type dopant into the deep body and channel regions of the cells to form annular source regions (third mask);
depositing a dielectric layer over the polysilicon layer;
selectively etching the dielectric layer to open in it contact windows to the deep body regions and to the source regions (fourth mask);
depositing a metal layer over the dielectric layer.
The necessity of respecting the mask alignment rules in two directions (parallel to the sides of the elementary cells) severely limits the possibility of scaling down the dimensions of the cells, to increase the scale of integration.
In the co-pending European Patent Application No. 94830288.0 a MOS-technology power device is disclosed wherein the elementary functional units are represented by stripes much more elongated in a longitudinal direction (xe2x80x9cthe Y directionxe2x80x9d) on the surface of the Nxe2x88x92 semiconductor layer than in a transversal direction (xe2x80x9cthe X directionxe2x80x9d); the source region comprises two regions elongated in the Y direction, and a plurality of transversal portions. In such a structure it is no longer necessary to respect the alignment rules of the contact mask with respect to the source mask along the X direction, since the transversal portions of the source region guarantee the short circuit between the source region and the deep body region even if the contact window opened in the dielectric layer has, in the X direction, the minimum dimension (xe2x80x9cfxe2x80x9d) allowed by the optical resolution of the photolithographic apparatus employed.
In the above mentioned patent application, it is said that the minimum dimension Lsmin of the stripe in the X direction is given by:
Lsmin=f+2a
where a is the minimum distance between the edge of the polysilicon layer and the edge of the contact window which, taking into account the alignment tolerance between the polysilicon mask and the contact mask, guarantees that the polysilicon gate is insulated from the source electrode.
Actually, another limit exists to the reduction of the dimension of the stripes along the X direction. The source mask is partially provided by the polysilicon and gate oxide layers, but further has a plurality of isles of photoresist over the middle portion of the stripes; this prevents the dimension of the stripes in the X direction from being below a value Lsminxe2x80x2 given by:
Lsminxe2x80x2=Apmin+2s
where Apmin is the minimum X dimension of the photoresist isles (minimum aperture in the dielectric layer) and coincide with the minimum dimension f allowed by the optical resolution of the photolithographic apparatus, and s is the minimum X dimension of each elongated portion of the source region, taking into account the alignment tolerance between the polysilicon mask and the source mask (i.e. between the edges of the polysilicon layer and the edges of the photoresist isles). By way of example, if for the source region a minimum dimension of 0.3 xcexcm in the X direction must be guaranteed, and the mask alignment tolerance is +0.2 xcexcm, s must be at least 0.5 xcexcm, and this must be considered the minimum dimension during the source mask layout design.
If Lsmin less than Lsminxe2x80x2, the actual limit to the reduction in the X dimension of the stripes is given by Lsminxe2x80x2.
In view of the state of the art disclosed, it is an object of the present invention to provide a process for the manufacturing of MOS-technology power devices which allows obtaining higher scales of integration with respect to the abovementioned prior art.
According to the present invention, such object is attained by means of a process for manufacturing high-density MOS-technology power devices, including the steps of:
a) forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type;
b) forming an insulating material layer over the insulated gate layer;
c) selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges delimiting respective uncovered surface stripes of the semiconductor material layer;
d) implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the insulating material layer to prevent the first dopant from being implanted in a central stripe of said uncovered surface stripes, to form pairs of heavily doped elongated source regions of the first conductivity type which extend along said two elongated edges of each elongated window and which are separated by said central stripe;
e) implanting a low dose of a second dopant of a second conductivity type along two directions which lie in said plane, and which are substantially symmetrically tilted at a second prescribed angle with respect to said orthogonal direction, to form doped regions of the second conductivity type each including two lightly doped elongated channel regions extending under the two elongated edges of each elongated window;
f) implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction, the insulating material layer acting as a mask, to form heavily doped regions substantially aligned with the edges of the elongated windows.
In the process according to the present invention, the implantation mask for the source regions coincides with the implantation mask for the channel regions and for the deep body regions of the elementary functional units; this is made possible by the use of implanting apparatus that allows the dopant to be implanted along directions tilted at angles ranging from 0xc2x0 to 60xc2x0 with respect to the direction orthogonal to a surface of the material wherein the dopant is to be implanted. Consequently, the tolerance on the dimension of the source regions is not determined by the mask alignment rules, but substantially by the tolerance of the thicknesses of three layers (gate oxide, polysilicon gate, insulating oxide), which is at least one order of magnitude lower. The dimension of the source region is therefore more finely controlled, and narrower elementary functional units can be formed.
Also according to the present invention, a high-density MOS-technology power device is provided including a plurality of elementary functional units formed in a semiconductor material layer of a first conductivity type covered by a conductive insulated gate layer sandwiched between two insulating layers, wherein each elementary functional unit comprises:
an elongated window formed in said insulated gate layer and in said two insulating layers, having two elongated edges and two short edges, said edges being sealed by insulating material sidewall spacers;
a heavily doped elongated deep body region of the second conductivity type formed in the semiconductor material layer and substantially aligned with the edges of the window;
two elongated channel regions of a second conductivity type formed in said semiconductor material layer and extending under the elongated edges of said window;
two elongated source regions of the first conductivity type formed in the deep body region along said elongated edges of the window.